In case of using this in some ST, you can get 16 MHz from shifter chip and 8 MHz from near FDC (before cutting), so no need for 74HC74.
How it works ? As said above, 75HC74 is 2-stage freq. divider, so we get 16 and 8 Mhz from 32 MHz system tact . Then with multiplexer 74HCT257 is selected what clock to pass to FDC chip. Simple logic will select 16MHz only if HD sense line (usually on pin 2 of floppy connector) is low (and it is low only when HD floppy is in and drive is selected). But during 3mS after sent step-pulse from FDC chip it will select 8 MHz too, even with HD floppy. And it means that steprate will remain 3mS, without SW correction (by usual HD circuits it goes by giving parameter 6mS in FDC commands, and it will be 3mS because of doubled tact). Task of monostable 74HCT221 is to serve exactly 3mS long pulse for our logic, and keep clock output at 8 MHz . That's all about...
4 chips are required, what is more than by usual non-auto-steprate circuits, but chips are cheap, and I think that it is worth because of easier usage.
Building in STE: you need to cut pin 18 (clock) of FDC chip (or line leading to it) and solder output of this circuit to that pin self. Step signal is on pin 16 of FDC chip. HD sense is usually on pin 2 of floppy connector. If not, then clock selection must be solved different. Of course, need to adjust accurate 3mS with R2 - it's easy: get some HD floppy with longer file(s) on and start reading of some file (copy, open or whatever). Adjust R2 so it will read whole file(s) without error and slowdowns.
Some extra possibilities with this circuit: reliable hyperformat - 11 sectors/track with HD floppies. Of course it is for some games cracked so. + easy possible 6 KB/track as is by couple. The point is in no need for SW steprate fix. So, this may be good for games, without need to patching code. I need some tests to perform and maybe to correct FloImg - so it can write SST images onto HD floppies...
PP Okt. 2009
